Monday, August 28, 2017
Switching Hyper v CSV Clustering from Software teaming to Hardware isolation
Switching Hyper v CSV Clustering from Software teaming to Hardware isolation
I wrote this article for several reasons. There are a lot of reasons why you may want to go from a Software team to Hardware, or Vice Versa. I make no comments as to why you would do either.
This is to say, There are some circumstances where you are better served with a Software team, and some where you will see better results with hardware and the NDIS driver.
I will leave the why up to you. However, If you have the need, here is a rough guide to get you though the conversion of a Software Teamed 2012 or 2016 Cluster conversion of your network, To hardware NICS and Isolation.
This article is high on text an low on screen shots. All I can do is apologize in advance.
Some Additional titles:
Converting the Windows Cluster from Software Teaming to Best Practices, Using Hardware Isolation.
Another title to this article could be switching from Software teaming to Hardware isolation for CSV clusters.
My software teamed cluster performs lousy.
Two Standards in two Documents
Why would you perform this change? You would do this if your using 1GB NICS for your cluster, and software teaming is not working well for you.
I have found that the network changes around 2012 may be better suited to 10GB NICS then 1GB NICS. I find the 1GB NICS aggregation may not always be the best way to setup a cluster, depending on the needs of the customer, and the type of software running.
I find that the original Network Best practices suit some customers from a maintenance perspective, as well as ease of understanding, when the IT persons are not full time network admins.
This article demands that your Storage Networks are on a separate switch from the Clustering Networks.
Furthermore, The Cluster Networks should be ideally isolated with Vlans, by Subnet, to prevent any collisions of packets from a unique subnet. If the Network is flat, That may not stop you from moving to this setup. Just know that some isolation is recommended. But, using a separate Subnet per Virtual network is still a must.
The Design of your network should be based on the Initial Configuration Guide for Hyper-V networks for a CSV cluster (2010).
If you do a Bing search for �network guide for Hyper-V clustering� , you will find this article,
Hyper-V: Live Migration Network Configuration Guide (2010)
And Bing �cluster guide for Hyper-V CSV cluster networks� and you should find:
Network Recommendations for a Hyper-V Cluster in Windows Server 2012 (2013)
The 2010 Documents lay out the Premise of Windows Clustering, with the goal of having CSV Live Migrations optimized. The 2013 Documents, Shows the embedded method of isolating the traffic within the Teamed interfaces.
The Opinion Section
Having been an Engineer lots of Hyper-V Cluster cases, the main reason for CSV cluster issues, was some form of mis-configuring the network, as per the best practices.
In 2012, we have now added the additional choices of using a software Microsoft Team and or LBFO options using scripting to send the traffic down specific virtual network adapters.
The change in server 2012 and 2016 has changed the perception of what can be done with the new technology. I now see the majority of Hyper-V networks using Microsoft teaming. Which is fine. Its fine, as long as you are using the virtual LANS; creating the isolation, along with the team. So the whole message of server 2012 and 2016 is Teaming and Isolation. What I am seeing all too often is just the teaming portion.
For this reason, I am bringing back the original specifications, to make the statement, that Isolation is the Key element to a CSV cluster. Teaming can be fine, But Proper Isolation comes first.
This means that if you are not a network person, and don�t have access to a network department to set things up for you, then you may want to stick with the original guidelines, which I am about to present to you. In this article, we are going to convert a Cluster from a Microsoft Teamed network, to a Vanilla Hardware Isolated, Cluster Network.
The assumption here is that all of your Network adapters have been thrown into a team or two. In addition, No VLANS were created to isolate your traffic. If there were VLANS created, you simply use power-shell to delete them. See the following script, changing the commands new-LbfoTeam, to remove-LBFOteam and etc�
Configuring networks 2/5
Words of Caution
You will start On a node, that is not being used by the cluster. We will make the changes to one node, at a time. When the first node is done, move to the next.
Please understand, This is a major change. You will likely have to take an outage to get this done across the whole cluster. I would make the changes on the first node (Node 1). Then shut all cluster nodes down, bringing up the node you converted. This will now be the primary cluster node, and as you update each additional node, they will come online, into the cluster represented by your Node 1
How to change you Cluster, One Node at a time
So here are the steps:
Pre Configuration
- Run Ipconfig /all > c:ipconfig.txt on all cluster nodes.
- Pull the MACS on Software Teamed NICS in the Server Manager->NIC Teaming-> Teams
- Save these files, even placing them in a spread, so you can match up the NICS you will be using. You need to make sure that you understand which NIC on each server will play each of the roles VMNIC, Live Migrate, CSV, Management, Storage, and Replication
- The columns of your spread are NIC name, NIC Description, MAC Address, OLD IP Address, New IP address, Cluster Workload and VLAN If Necessary
- Remember not to record NICS that have parenthesis around them or are multi-plex adapters. These will be going away. We will only rely on physical adapters.
- The Rows of your Spread are as follows:
- NODE X
- VMNIC Go to Programs and Features and right click the Network adapter management application.
- Select the �Change� option
- Add NDIS if Broadcom, or whatever the 4 letter acronym is for advanced service of the NIC brand installer.
That�s it. Once you have done the second machine, make sure you can ping across to the other NIC on host1.
As long as you pass the ping test, you may move to changing the other Nodes in the cluster.
Once you have completed the changes, and all machines ping properly, you may restart the nodes in a round robin style if you have any kinks
The only thing left to do, Is to set your priorities for the networks. The priorities are in the center pane of cluster manager. Choose network in the left selection plane.
Workloads
The settings should be changed to the following:
- VMNIC � NONE (dedicated to VMS)
- LIVE MIGRATE � Cluster Communication only
- CSV � Cluster Communication only
- Management- client only
- Replication- Cluster and client
- Storage1, 2 etc. � N/A no cluster communication
And that�s it. Once you have that established, your cluster will now be working on physical NICS only.
Now with the NICS you have left, you may go back and add selective hardware teaming where it makes sense. No Teaming on Storage NICS. Honestly, it may be better to wait to see if you have any area of weakness. For Example, If the VMs seem slow during intense workdays, you may remove the VMNIC, from Hyper-V, Team it, and then put the multiplexor back in as the VMNIC used for Hyper-V VMs.
I hope this has been helpful. Please remember that this works automatically, because the Cluster is able to identify NICS on different servers, and automatically matches them to the same subnet. The NICs from the various servers will show up together in the network tab, because they are on the same subnet. As such, the cluster knows that they will be performing a specific job in the cluster, based on the settings laid out in this article.
This is not better or worse then software teaming, but it may be the right choice for some IT teams, who are more familiar with hardware NIC assignments as part of their Job description.
Also please understand the days of teaming with 1GB NICS is coming to a close. Very quickly 10GB NICS are becoming the standard. The difference in these setups becomes MOOT when your no longer using 1GB adapters for clustering.
Thank you,
Have a nice Day.
(ex. no Subnet) - LIVE MIGRATE (ex. 10.10.11.x)
CSV (ex. 10.10.12.x) HOST (ex. 10.10.13.x) - Replication (ex. 10.10.14.x)
- So your Subnets need to be assigned by #6 above. All VMNICS wont have an IP because they will all be dedicated to the Hyper-V switch. The easiest way to express this is to explain that Every Live Migrate will be on the 10.10.11 network. Every CSV will be on the 10.10.12 network. Every host will be on the 10.10.13 network. Every Replication will be on the 10.10.14 network. Every host will have a dedicated NIC for each of these networks.
- Replication above would be Ideal. If you don�t have enough NICS to have this network, then its ok. This NIC may also be called a Storage NIC. IF so, this NIC will Have MS Client sharing disabled, and uncheck register in DNS for this NIC.
- the Cluster workload on your spread can be populated from the section below called workloads
Hopefully, these tidbits have helped you prepare for the actual work, because here we go. This will need to happen on every cluster Node.
Configuration
- Go into every VM and change the NIC to not configured
- Remove all Network adapters from the Software teams.
- Delete the Virtual Hyper-v Network � if external
- Verify that all virtual NICS are gone. Restart server if they are not.
- Label 5 (or more) NICS as follows: (minimum 4)
- VMNIC
- LIVE MIGRATE
- CSV
- Management
- Replication
- Storage1, 2 etc.
- VMNIC Go to Programs and Features and right click the Network adapter management application.
- NODE X
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Supporting a Microcontroller Course with Hardware
Supporting a Microcontroller Course with Hardware
If you have come to this article for a prescription then I am afraid you are in the wrong place. I have structured this piece as a list of questions you need to answer to obtain the microcontroller that really suits your wants and needs. I have included the answers that work for me at the end to show how I have answered my needs.
Teaching microcontrollers always starts with the architecture. Sadly this is hardly ever a process that starts with a clean sheet. Each university or company typically has historical investments in a few preferred architectures and sticks to them like glue. Opportunities to change existing courses should always be carefully weighed for the costs and benefits.
If you are starting from a clean sheet, or reconsidering existing teaching let me urge you to consider the ARM architecture for one incredibly good reason: the prediction that one ARM processor will be manufactured per person per year by 2014 (EE Times). There are already billions out there in the world. If you are not teaching ARM consider very carefully whether you are doing the right thing by your students by leaving this very valuable training out of their studies. If you want other reasons consider you can get ARM powered chips for the same prices as 8 and 16 bit microcontrollers with comparable peripherals that have 32 bit datapaths and high clock speeds from many manufacturers! Access to development kits mounting ARM Cortex-M devices with programmers/debuggers can cost as little as $12.[It should be no secret that I am an admirer of ARM cores and have been working with ARM for some time now]
What are the course choices?
Excluding budget constraints and existing equipment and if the number of hours in the course is fixed then we can classify courses into three types. These types are based on where the weight of the learning outcomes are placed as well as the existence of suitable hardware and software support. The three categories are:
- "Bare metal" (bare chips and a programmer/debugger) - This is one of the best ways of achieving learning outcomes that include basic hardware requirements of microcontrollers i.e. clocks, resets, capacitive decoupling, etc. Coding will consider the booting of the microcontroller as well as code to support any peripherals.
- Interfacing (a PCB with a few LEDs and switches, probably a clock crystal) - Learning outcomes mainly consist of building interfaces to other peripherals and hardware and advanced coding to support the peripherals.
- Embedded Software (a loaded PCB where every interface or IO connected to an appropriate demonstration peripheral) - This emphasizes coding, probably including a suitable RTOS or algorithms development for embedded systems.
On Chip Debugging. Can the actual ASM code and data in RAM be observed while the microprocessor is executing software?It can be very easy to end up with hardware that will not support any visibility into the microprocessor/microcontroller as its executes software. In my opinion this damages and interferes with your students ability to understand and experiment with code inside the microcontroller. In my opinion on chip debugging is a basic pedagogic requirement for any course, not a "value added extra" [NB It is possible to design courses around this limitation but, really, in the 21st century why should you have to? And why should your students be limited in this way?]
Practical considerations when choosing a course
The main point when considering the three main levels of microcontroller courses you are thinking of teaching is whether you have any electronic laboratory capability, i.e. lab equipment (PC, oscilloscope, function generator, power supply and parts) and trained teaching and support staff or not.
If you have a lab then you can look at implementing any of the levels. If not then go for Embedded Software straight away or establish the lab later. "Bare Metal" and Interfacing are not for you!
As a practical point for "Bare Metal" courses if chips are not available or convertible to a DIP package choose another architecture to teach.
If you have the lab then the investment in development kits may be a factor. The fully featured kits necessary for Embedded Software are the most expensive, and the least effective at supporting the Interfacing course. At best a few GPIO are available for your students to play with.
Homebrew hardware/Custom hardware or commercial? This is always a tricky one and best left to your judgment. A few points to consider are:
- Have you used the micro before? If not a commercial kit may help, at least for the first few years.
- Do you really need a custom system? If you are doing something specialist or have an existing investment in expansion hardware then a custom system can be a part of a really interesting and challenging course.
- Custom hardware needs designing and then supporting i.e. repairing, updating, etc. and often proves much more expensive over time than commercial kit.
Bear in mind the three "levels" of course I have just discussed then we can seriously look at which architecture we should support from two points of view: Pedagogic (teaching) and Practical.
Pedagogic
- Are the functions of the CPU core easy to separate into a simple subset? All real cores tend to have advanced features and blend certain activities due to the need for speed but for training purposes can you keep them separate?
- Memory access. This is pretty important and in my opinion it should be a single memory space not paged and the ability to directly execute on data in the memory should be limited - i.e. register math
- Is the architecture RISC or CISC? Teaching any CISC architecture is typically only sensible from a software programmers point of view and even then it doesnt lend itself to a structured course. I would firmly suggest that a RISC form the basis of your courses
Practical
- Confidence/Experience - If you have had success with a design or device then a new device represents a big unknown in terms of software and hardware. Remember those unexpected Errata?
- Documentation - Typically for a university a huge amount of existing documentation and notes that have built up around the architecture. Think of all the tutorials and lectures that need rewriting!
- Staff training - Your lab helpers have to know how things work, i.e. does the debugger connect every time? Do you have to reboot the PC if the thing hangs? Does the software have any quirks? (perhaps what quirks does the software have)
What hardware?
Here are the factors that I think are most important in choosing a development kit. This is where ARM technologies really score - compared to proprietary architectures there is a real diversity of choice of chip manufacturer with about every possible peripheral included:
- Cost - labs full of development kit adds up pretty pricey
- Programmer/debugger cost - see above. Dont forget that many programmer/debuggers are NOT bundled with the development boards. Also if you want your own students to have their own personal boards they are going to need programmer/debuggers.
- Software - how easy is it to access the compilers and debuggers
- Robustness - students are pretty hard on kit. How much work are you going to have to do to harden the boards electronically and physically?
- On chip peripherals - if you are going to teach standard peripherals like USARTs or I2C then make sure they are included in your micro
What software?
We then need to consider the programming environment. Again ARM has a real breadth of choice of IDEs and compilers for ARM based microcontrollers. The following points should be born in mind:
- Is there a free version for students, and if so how limited is it?
- Is the full version terribly expensive and under what conditions can it be accessed? Hardware companies have an easier choice when software than purely software companies as for them the software is not their core business.
- How easy is it to support? There are plenty of development IDEs that require Administrator access to run or access the debugger and are often very unstable or full of bugs*.
My choices
[These choices are influenced by my relationship with ARM but they may help you work through your own choices. It is important to declare interests.]
The two courses I am planning to support are two Interfacing courses. I also have an eye on project work which involves microcontrollers. Both courses are established and apply different requirements on the hardware that is going to be used.
What architecture?
Looking at ARM architectures for what I wish to achieve it is clear that we should be looking at the current generation of cores, i.e. the Cortex M or A series. The M stands for microcontroller or mixed signal and A for application. From an architectural point of view the simpler M series are clearly preferable. We are looking at Interfacing and the available M series parts are much more suited to that goal in terms of their peripherals. For Embedded Software high end M parts or A parts would be just fine. For bare metal work there are some small pin count M parts which can be adapted to a DIP pinouts but it is more challenging to use ARM for that type of course.
IDE, compiler & debugger
I am looking at using the uVision IDE from Keil (owned by ARM) because:
- It is compatible with a very wide range of devices from many manufacturers so you are not tied to any one single company. This will allow a lot of reuse of notes if the target microcontroller is withdrawn or updated
- It has compilers, assemblers, and on chip debugging facilities
- There is the essential free version for anyone with code size limits which are well under anything you are likely to need - 32kb of code max (MDK-ARM Lite). [ARM typically have always supported universities strongly so a donation of the full version for internal use in teaching and research may be very possible - talk to them]
- Keil tools are also pretty well behaved as windows programs and receive regular updates to fix bugs. Other IDEs I have used dont even regard some problems as bugs at all!
- Keil donations are accessible via ARM which doesnt have the sale of development software as its core business with the implications for donations.
Development kits
The two courses have quite different requirements. One course needs two boards:
- One for the students to own by themselves - cost is a very important consideration
- One with a large amount of IO for the labs and direct access to a memory mapped IO space
- Both should not have too many built in demonstration hardware (it pushes up the cost and wastes valuable IO capability)
Resources to help find suitable ARM development platforms can be found on the university program section of ARMs website. Here are the highlights of the development boards I have considered:
Low cost student owned development board
- Micro is the ST STM32F100RB, a Cortex-M3 running at 24MHz with 128kb of flash and 8kb of RAM
- On chip peripherals: 1x ADC, 2x DAC, Timers, 2x I2C, 3x USART, 2x SPI and something called CEC. There is also a DMA unit
- The programmer/debugger is an ST-Link built onto the top section of the board. It can also be used to program and debug other ST STM32 ARM based microcontrollers using the ARM Serial Wire Debug (SWD) bus
- The ST-Link is Keil uVision compatible for programming and on chip debugging
- $12 as of the 11th of July from DigiKey
- LPCXpresso is both an IDE (powered by code_red technology) and a set of development boards for NXPs LPC ARM based microcontrollers
- Supports various LPC families of microcontrollers based on the ARM Cortex-M3 and simpler Cortex-M0
- Built onto a (one time detachable) NXP LPC-Link programmer/debugger that is supported by the code_red based IDE
- $29.95 as of the 11th of July from DigiKey. Note the variety of parts available as well as more complex and higher cost LPCXpresso compatible boards
For consideration: ARM NXP mbed- Needs no special programming hardware or any locally installed software as it is programmed from the mbed website using a web browser. Appears to the PC as a USB stick where if you place a file on it and press a button it programs itself
- Seriously limited for my purposes by the lack of On Chip Debugging and simplified programming system [NB not due to the NXP micro but due to the requirement to not need locally installed software]
- This was not a serious candidate for the level of education that I wish to engage in however is a very serious player for courses in high school or the first year of University
- Does not come with a "standard" programmer/debugger
- $60 as of the 11th of July from DigiKey
Lab board with native USB connectivity and external memory interface
[NB This board is a Keil product due to my relationship with ARM, not that there are not excellent candidates from other providers.]
[NNB Keil does make excellent boards though!]
- Micro is the Fujitsu FM3 MB9BF506, a Cortex-M3 running at 80MHz with 512kb of flash and 64kb of RAM
- Full physical access to each and every pin on the device
- On chip peripherals: USB2.0 Device and Host, 2x CAN, 8 channel DMA, External Bus IF supporting 8/16 bit SRAM, NOR and NAND flash with up to 8 chip selects, 8x USART/CSIO/LIN/I2C Serial ports, 8x Timers, 2x Multi-Function Timers, CRC Accelerator and 3x 16 channel ADCs
- Apart from a few LEDs, switches, one potentiometer and the USB device and host port all the rest of the IO is accessible via the two fantastic 0.1" pitch dual row sockets. 0.1" pitch headers are the best educational header being sufficiently small to be convenient but strong to take abuse and rough handling
- Programmed and debugged by the ULINK-ME programmer from Keil (not shown). [NB This is not available for general purchase, only with new kits so be sure to make sure it is included]
- Compatible with uVision IDE from Keil [NB Obvious, perhaps]
- $100 as of the 11th of July from DigiKey (I havent linked it here as DigiKey doesnt seem to sell the version with the bundled ULINK-ME but I cant be sure. Buyer Beware)
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